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dual-channel, 2.5 kv isolators with integrated dc-to-dc converter data sheet adum5200 / adum5201 / adum5202 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009-2012 analog devices, inc. all rights reserved. features iso power integrated, isolated dc-to-dc converter regulated 3.3 v or 5 v output up to 500 mw output power dual, dc-to-25 mbps (nrz) signal isolation channels 16-lead soic package with 7.6 mm creepage high temperature operation: 105c maximum high common-mode transient immunity: >25 kv/s safety and regulatory approvals ul recognition 2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a) vde certificate of conformity (pending) iec 60747-5-2 (vde 0884, part 2):2003-01 v iorm = 560 v peak applications rs-232/rs-422/rs-485 transceivers industrial field bus isolation power supply start-up bias and gate drives isolated sensor interfaces industrial plcs general description the adum5200 / adum5201 / adum5202 1 are dual-channel digital isolators with isopower?, an integrated, isolated dc-to-dc converter. based on the analog devices, inc., i coupler? technology, the dc-to-dc converter provides up to 500 mw of regulated, isolated power at either 5.0 v or 3.3 v from a 5.0 v input supply, or 3.3 v from a 3.3 v supply at the power levels shown in table 1. these devices eliminate the need for a separate, isolated dc-to-dc converter in low power isolated designs. the i coupler chip scale transformer technology is used to isolate the logic signals and for the magnetic components of the dc-to-dc converter. the result is a small form factor, total isolation solution. the adum5200 / adum5201 / adum5202 isolators provide two independent isolation channels in a variety of channel configurations and data rates (see the ordering guide for more information). iso power uses high frequency switching elements to transfer power through its transformer. special care must be taken during printed circuit board (pcb) layout to meet emissions standards. see the an-0971 application note for board layout recommendations. functional block diagrams 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 osc rect 2-channel i coupler core v dd1 reg gnd 1 v ia /v oa v ib /v ob rc in rc sel v e1 /nc gnd 1 v iso gnd iso v ia /v oa v ib /v ob nc v sel v e2 /nc gnd iso adum5200/ adum5201/ adum5202 07540-001 figure 1. 3 4 14 13 adum5200 07540-002 v ia v ib v oa v ob figure 2. adum5200 3 4 14 13 adum5201 07540-003 v ia v ob v oa v ib figure 3. adum5201 3 4 14 13 adum5202 07540-004 v oa v ob v ia v ib figure 4. adum5202 table 1. power levels input voltage (v) output voltage (v) output power (mw) 5.0 5.0 500 5.0 3.3 330 3.3 3.3 200 1 protected by u.s. patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
adum5200/adum5201/adum5202 data sheet rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 genera l description ......................................................................... 1 functional block diagrams ............................................................. 1 revision history ............................................................................... 2 s pecifications ..................................................................................... 3 electrical characteristics 5 v primary input supply/ 5 v secondary isolated supply ................................................... 3 electrical characteristics 3.3 v primary input supply/ 3.3 v secondary isolated supply ................................................ 5 electrical characteristics 5 v primary input supply/ 3.3 v secondary isolated supply ................................................ 7 package characteristics ............................................................... 9 regulatory information ............................................................... 9 insulation and safety - related specifications ............................ 9 iec 60747 - 5 - 2 (vde 0884, part 2):2003 - 01 insulation characteristics ............................................................................ 10 recommended operating conditions .................................... 10 absolute maximum ratings .......................................................... 11 esd caution ................................................................................ 11 pin configurations and function descriptions ......................... 12 truth table .................................................................................. 14 typical performance characteristics ........................................... 15 terminology .................................................................................... 18 applications information .............................................................. 19 pcb layout ................................................................................. 19 start - up behavior ....................................................................... 19 emi considerations ................................................................... 20 propagation delay parameters ................................................. 20 dc correc tness and magnetic field immunity .......................... 20 power consumption .................................................................. 21 current limit and thermal overload protection ................. 22 power considerations ................................................................ 22 thermal analysis ....................................................................... 23 increasing available power ....................................................... 23 insulation lifetime ..................................................................... 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 5 /12 rev. a to rev. b created hyperlink for safety and regulatory approvals entry in features section ................................................................. 1 updated outline dimensions ....................................................... 25 9 /1 1 rev. 0 to rev. a changes to product title, features section, and general d escription section .......................................................................... 1 added table 1; renumbered sequentially .................................... 1 changes to specifications section .................................................. 3 changes to table 19 and table 20 ................................................ 11 changes to pin 5 description, table 21 ....................................... 12 changes to pin 5 description, table 22 ....................................... 13 changes to pin 5 description, table 23 and table 24 ............... 1 4 changes to figure 9 to figure 11 .................................................. 1 5 added figure 17 and figure 18; renumbered sequentially ..... 1 6 changes to figure 19 and figure 20 ............................................ 1 6 changes to terminology section ................................................. 1 8 changes to applications information section ........................... 19 added start - u p behavior se ction ................................................ 19 changes to emi considerations section .................................... 20 10/08 revision 0: initial version
data sheet adum5200/adum5201/adum5202 rev. b | page 3 of 28 specifications electrical character istics 5 v primary input su pply/5 v secondary i solated supply all typical specifications are at t a = 25c, v dd1 = v sel = v iso = 5 v. minimum/maximum specifications apply over the entire recommended operation range which is 4.5 v v dd1 , v sel , v iso 5.5 v ; and ? 40c t a + 105c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels , unless otherwise noted . table 2 . dc -to - dc converter static specification s parameter symbol min typ max unit test conditions dc - to - dc converter supply setpoint v iso 4.7 5.0 5.4 v i iso = 0 ma line regulation v iso (line) 1 mv/v i i so = 50 ma, v dd1 = 4.5 v to 5.5 v load regulation v iso (load) 1 5 % i iso = 10 ma to 90 ma output ripple v iso (rip) 75 mv p -p 20 mhz bandwidth, c bo = 0.1 f || 10 f, i iso = 90 ma output noise v iso (n oise ) 200 mv p -p c bo = 0.1 f||10 f, i iso = 90 ma switching frequency f osc 180 mhz pw modulation frequency f pwm 625 khz output sup ply i iso (max) 100 ma v iso > 4.5 v efficiency at i iso (max) 34 % i iso = 100 ma i dd1 , no v iso load i dd1 (q) 8 22 ma i dd1 , full v iso load i dd1 (max) 290 ma table 3 . dc -to - dc converter dynamic specifications parameter symbol 1 mbps a grade or c grade 25 mbps c grade unit test conditions min typ max min typ max supply current input no v iso load adum5200 i dd1 6 34 ma adum5201 i dd1 7 38 ma adum5202 i dd1 7 41 ma available to load adum5200 i iso (load) 100 94 ma adum5201 i iso (load) 100 92 ma adum5202 i iso (load) 100 90 ma table 4 . switching specifications parameter symbol a grade c grade unit test conditions min typ max min typ max switching specifications data rate 1 25 mbps within pwd limit propagation delay t phl , t plh 55 100 45 60 ns 50% i nput to 50% output pulse width distortion pwd 40 6 ns |t plh ? t phl | change vs. temperature 5 ps/c pulse width pw 1000 40 ns within pwd limit propagation delay skew t psk 50 15 ns between any two units channel matchi ng codirectional 1 t pskcd 50 6 ns opposing direction al 2 t pskod 5 0 15 ns 1 7 co directional channel matching is the absolute value of the difference in propagation delays between any two channels with inpu ts on the same side of the isolation barrier. 2 opposing directional channel matching is the absolute value of the difference in pr opagation delays between any two channels with inputs on opposing sides of the isolation barrier.
adum5200/adum5201/adum5202 data sheet rev. b | page 4 of 28 table 5 . input and output characteristics parameter symbol min typ max unit test conditions dc specifications logic high input threshold v ih 0.7 v iso or 0 .7 v dd1 v logic low input threshold v il 0.3 v iso o r 0.3 v dd 1 v logic high output voltages v oh v dd 1 ? 0. 3 or v iso ? 0. 3 5.0 v i ox = ?20 a, v ix = v ixh v dd 1 ? 0. 5 or v iso ? 0. 5 4.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl undervoltage lockout v dd1 , v ddl , v i so s uppl ies positive going threshold v uv+ 2.7 v negative going threshold v uv ? 2.4 v hyster e sis v uvh 0.3 v input currents per channel i i ?20 +0.01 +20 a 0 v v i x v dd x ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90 % common - mode transient immunity 1 |cm| 25 3 5 kv/s v ix = v dd 1 or v iso , v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1. 0 mbps 1 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0. 7 v dd1 or 0. 7 v iso for a high out put or v o < 0. 3 v dd1 or 0. 3 v iso for a low output. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges.
data sheet adum5200/adum5201/adum5202 rev. b | page 5 of 28 electrical character istics 3.3 v primary input supply/3.3 v seconda ry isolated supply all typical specifications are at t a = 25c, v dd1 = v iso = 3.3 v , v sel = gnd iso . minimum/maximum specifications apply over the entire recommended operation range which is 3.0 v v dd1 , v sel , v iso 3.6 v ; and ? 40c t a + 105c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels , unless otherwise noted . table 6 . dc -to - dc converter static specification s pa rameter symbol min typ max unit test conditions dc - to - dc converter supply setpoint v iso 3.0 3.3 3. 6 v i iso = 0 ma line regulation v iso (line) 1 mv/v i iso = 30 ma, v dd1 = 3.0 v to 3.6 v load regulation v iso (load) 1 5 % i iso = 6 ma to 54 ma ou tput ripple v iso (rip) 50 mv p -p 20 mhz bandwidth, c bo = 0.1 f||10 f, i iso = 54 ma output noise v iso (n oise ) 130 mv p -p c bo = 0.1 f||10 f, i iso = 54 ma switching frequency f osc 180 mhz pw modulation frequency f pwm 625 khz output supply i i so (max) 60 ma v iso > 3 v efficiency at i iso (max) 3 4 % i iso = 60 ma i dd1 , no v iso load i dd1 (q) 6 15 ma i dd1 , full v iso load i dd1 (max) 175 ma table 7 . dc -to - dc converter dynamic specifications parameter symbol 1 mbp s a grade or c grade 25 mbps c grade unit test conditions min typ max min typ max supply current input no v iso load adum5200 i dd1 4 23 ma adum5201 i dd1 4 25 ma adum5202 i dd1 5 27 ma available to load adum5200 i iso (load) 60 56 ma adum5201 i iso (load) 60 55 ma adum5202 i iso (load) 60 54 ma table 8 . switching specifications parameter symbol a grade c grade unit test conditions min typ max min typ max switching specifications data rate 1 25 mbps within pwd limit propagation delay t phl , t plh 60 100 45 60 ns 50% input to 50% output pulse width distortion pwd 40 6 ns |t plh ? t phl | change vs. temperature 5 ps/c pulse width pw 1000 40 ns within pwd limit propagation delay skew t psk 50 45 ns between any two units channel matching codirectional 1 t pskcd 50 6 ns opposing directional 2 t pskod 50 15 ns 1 7 codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with in puts on the same side of the isolation barrier. 2 opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
adum5200/adum5201/adum5202 data sheet rev. b | page 6 of 28 table 9 . input and output characteristics parameter symbol min typ max unit test conditions dc specifications logic high input threshold v ih 0.7 v iso or 0.7 v dd1 v logic low input threshold v il 0.3 v iso or 0.3 v dd1 v logic high output volt ages v oh v dd1 ? 0. 3 or v iso ? 0.3 3.3 v i ox = ?20 a, v ix = v ixh v dd1 ? 0.5 or v iso ? 0.5 3.1 v i ox = ?4 ma, v ix = v ixh logic low output voltages v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.0 0.4 v i ox = 4 ma, v ix = v ixl undervoltage lockout v dd1 , v ddl , v iso s upplies positive going threshold v uv+ 2.7 v negative going threshold v uv ? 2.4 v hyster e sis v uvh 0.3 v input currents per channel i i ? 2 0 +0.01 + 2 0 a 0 v v ix v dd x ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 1 |cm| 25 35 kv/s v ix = v dd1 or v iso , v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.0 mbps 1 |cm| is the maximum com mon - mode voltage slew rate that can be sustained while maintaining v o > 0. 7 v dd1 or 0. 7 v iso for a high out put or v o < 0. 3 v dd1 or 0. 3 v iso for a low output. the common - mode voltage slew rates apply to both rising and falling common - mode voltage ed ges.
data sheet adum5200/adum5201/adum5202 rev. b | page 7 of 28 electrical character istics 5 v primary input su pply/3.3 v secondary isolat ed supply all typical specifications are at t a = 25c, v dd1 = 5.0 v, v iso = 3.3 v , v sel = gnd iso . minimum/maximum specifications apply over the entire recommended operation range which is 4.5 v v dd1 5.5 v , 3.0 v v iso 3.6 v ; and ? 40c t a + 105c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels , unless otherwise note d. table 10. dc -to - dc converter static spe cification s parameter symbol min typ max unit test conditions dc - to - dc converter supply setpoint v iso 3.0 3.3 3.6 v i iso = 0 ma line regulation v iso (line) 1 mv/v i iso = 50 ma, v dd1 = 3.0 v to 3.6 v load regulation v iso (load) 1 5 % i iso = 6 m a to 54 ma output ripple v iso (rip) 50 mv p -p 20 mhz bandwidth, c bo = 0.1 f||10 f, i iso = 90 ma output noise v iso (n oise ) 130 mv p -p c bo = 0.1 f||10 f, i iso = 90 ma switching frequency f osc 180 mhz pw modulation frequency f pwm 625 khz ou tput supply i iso (max) 100 ma v iso > 3 v efficiency at i iso (max) 3 0 % i iso = 9 0 ma i dd1 , no v iso load i dd1 (q) 5 15 ma i dd1 , full v iso load i dd1 (max) 230 ma table 11. dc -to - dc converter dynamic specifications parame ter symbol 1 mbps a grade or c grade 25 mbps c grade unit test conditions min typ max min typ max supply current input no v iso load adum5200 i dd1 5 22 ma adum5201 i dd1 5 23 ma adum5202 i dd1 5 24 ma available to load adum5200 i iso (load) 100 96 ma adum5201 i iso (load) 100 95 ma adum5202 i iso (load) 100 94 ma table 12 . switching specifications parameter symbol a grade c grade unit te st conditions min typ max min typ max switching specifications data rat e 1 25 mbps within pwd limit propagation delay t phl , t plh 60 100 45 60 ns 50% input to 50% output pulse width distortion pwd 40 6 ns |t plh ? t phl | change vs. temperature 5 ps/c pulse width pw 1000 40 ns within pwd limit propagation delay skew t psk 50 15 ns between any two units channel matching codirectional 1 t pskcd 50 6 ns opposing directional 2 t pskod 50 15 ns 1 7 codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with in puts on the same side of the isolation barrier. 2 opposing directional channel matching is the absolute value of the differ ence in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
adum5200/adum5201/adum5202 data sheet rev. b | page 8 of 28 table 13. input and output characteristics parameter symbol min typ max unit test conditions dc specifications logic high input threshold v ih 0.7 v iso or 0.7 v dd1 v logic low input threshold v il 0.3 v iso or 0.3 v dd1 v logic high output voltages v oh v dd1 ? 0.2, v iso ? 0.2 v dd1 or v iso v i ox = ?20 a, v ix = v ixh v dd1 ? 0.5 or v iso ? 0.5 v dd1 ? 0.2 or v iso ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low output voltages v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.0 0.4 v i ox = 4 ma, v ix = v ixl undervoltage lockout v dd1 , v ddl , v iso supplies positive going threshold v uv+ 2.7 v negative going threshold v uv? 2.4 v hysteresis v uvh 0.3 v input currents per channel i i ?20 +0.01 +20 a 0 v v ix v ddx ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common-mode transient immunity 1 |cm| 25 35 kv/s v ix = v dd1 or v iso , v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.0 mbps 1 |cm| is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.7 v dd1 or 0.7 v iso for a high output or v o < 0.3 v dd1 or 0.3 v iso for a low output. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
data sheet adum5200/adum5201/adum5202 rev. b | page 9 of 28 package characteristics table 14. thermal and isolation characteristics parameter symbol min typ max unit test conditions resistance and capacitance resistance (input-to-output) 1 r i-o 10 2 capacitance (input-to-output) 1 c i-o 2.2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction to ambient thermal resistance ja 45 c/w thermocouple located at the center of the package underside; test conducted on a 4-layer board with thin traces 3 thermal shutdown threshold ts sd 150 c t j rising hysteresis ts sd-hys 20 c 1 this device is considered a 2-terminal device; pin 1 through pin 8 are shorted together, and pin 9 through pin 16 are shorted together. 2 input capacitance is from any input data pin to ground. 3 refer to the power considerations section for thermal model definitions. regulatory information the adum5200 / adum5201 / adum5202 are approved by the organizations listed in table 15. refer to table 20 and the insulation lifetime section for more information about the recommended maximum working voltages for specific cross-insulation waveforms and insulat ion levels. table 15. ul 1 csa vde (pending) 2 recognized under ul 1577 component recognition program 1 approved under csa component acceptance notice #5a certified according to iec 60747-5-2 (vde 0884, part 2):2003-01 2 single protection, 2500 v rms isolation voltage testing was conducted per csa 60950-1-07 and iec 60950-1 2 nd ed. at 2.5 kv rated voltage basic insulation at 600 v rms (848 v peak ) working voltage reinforced insulation at 250 v rms (353 v peak ) working voltage basic insulation, 560 v peak file e214100 file 205078 file 2471900-4880-0001 1 in accordance with ul 1577, each adum5200 / adum5201 / adum5202 is proof tested by applying an insulation test volt age 3000 v rms for 1 second (current leakage detection limit = 10 a). 2 in accordance with iec 60747-5-2 (vde 0884 part 2):2003-01, each adum520x is proof tested by applying an insulation test volta ge 1590 v peak for 1 second (partial discharge detection limit = 5 pc). the asterisk (*) marking br anded on the component designates iec 60747-5-2 (vde 0884, part 2 ):2003-01 approval. insulation and safety-related specifications table 16. critical safety-related di mensions and material properties parameter symbol value unit test conditions/comments rated dielectric insulation voltage 2500 v rms 1-minute duration minimum external air gap l(i01) 8.0 mm distance measured from input terminals to output terminals; shortest distance through air along the pcb mounting plane, as an aid to pc board layout minimum external tracking (creepage) l(i02) 7.6 mm measured from input termin als to output terminals, shortest distance path along body minimum internal distance (internal clearance) 0.017 min mm distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303, part 1 isolation group iiia material group (din vde 0110, 1/89, table 1)
adum5200/adum5201/adum5202 data sheet rev. b | page 10 of 28 iec 60747 - 5 - 2 (vde 0884, part 2) :2003 - 01 i nsulation characteri stics these isolators are suitable for reinforced electrical isolation only w ithin the safety limit data. maintenance of the safety data is ensured by the protective circuits. the asterisk (*) marking branded on the component s de signa tes iec 60747 - 5 - 2 (vde 0884, part 2):2003 - 1 approval. table 17. vde charact eristics description conditions symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii c limatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 560 v peak input - to - output test voltage, method b1 v iorm 1.875 = v pd ( m ) , 100% production test, t ini = t m = 1 sec, partial dis charge < 5 pc v pd (m) 1050 v peak input - t o - output test voltage, method a after environmental tests subgroup 1 v iorm 1.5 = v pd ( m ) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd ( m ) 8 40 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pd ( m ) , t ini = 60 sec, t m = 1 0 sec, partial discharge < 5 pc v pd ( m ) 672 v peak highest allowable overvoltage v iotm 4000 v peak withstand isolation voltage 1 minute withstand rating v iso 2500 v rms surge isolation voltage v peak = 6 kv, 1.2 s rise time, 50 s , 50% fall time v iosm 6 000 v peak safety limiting values maximum value allowed in the event of a failure (see figure 5 ) case temperature t s 150 c side 1 i dd1 current i s1 555 m a insulation resistance at t s v io = 500 v r s >10 9 ? 0 100 200 300 400 500 600 0 50 100 150 200 ambient temperature (c) safe operating v dd1 current (ma) 07540-005 figure 5 . thermal derating curve, dependence of safety limiting values on case temperature, per din en 60747 - 5- 2 recommended operatin g conditions table 18. parameter symbol min max unit operating temperature 1 t a ?40 + 105 c supply voltages 2 v dd1 @ v sel = 0 v v dd 1 3.0 5.5 v v dd1 @ v sel = v iso v dd 1 4.5 5.5 v 1 operation at 105c requires reduction of the maximum load current as specified in table 19. 2 each voltage is relative to its respective ground.
data sheet adum5200/adum5201/adum5202 rev. b | page 11 of 28 absolute maximum rat ings t a = 25c, unless otherwise noted. table 19. parameter rating storage temperature range (t st ) ? 55c to +150c ambient operating temperature range (t a ) ?40c to +105c supply voltages (v dd 1 , v iso ) 1 ?0.5 v to +7.0 v input voltage (v ia , v ib , rc in , rc sel , v sel ) 1 , 2 ?0.5 v to v ddi + 0.5 v output voltage (v oa , v ob ) 1 , 2 ?0.5 v to v ddo + 0.5 v average output current per pin 3 ?10 ma to +10 ma c ommon - mode transients 4 ?100 kv/s to +100 kv/s 1 each voltage is relative to its respective ground. 2 v ddi and v ddo refer to the supply voltages on the input and output sides of a given channel, respectively. see the pcb layout section. 3 see figure 5 for maximum rated current values for various temperatures. 4 common - mode transients exceeding the absolute maximum slew rate may cause latch - up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above t hose indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution table 20. maximum continuous wor king voltage supporting 50 - year minimum lifetime 1 parameter max unit applicable certification ac voltage, bipolar waveform 424 v peak all certifications, 50 - year operation ac voltage, unipolar waveform basic insulation 600 v peak working voltage , 50 - ye ar operation reinforced insulation 353 v peak working voltage per iec 60950 - 1 dc voltage basic insulation 600 v peak working voltage , 50- year operation reinforced insulation 353 v peak working voltage per iec 60950 - 1 1 refers to the continuous voltag e magnitude imposed across the isolation barrier. see the insulation lifetime section for more information.
adum5200/adum5201/adum5202 data sheet rev. b | page 12 of 28 pin configurations a nd function descript ions v dd1 1 gnd 1 2 v ia 3 v ib 4 v iso 16 gnd iso 15 v oa 14 v ob 13 rc in 5 nc 12 rc se l 6 v se l 1 1 nc 7 v e2 10 gnd 1 8 gnd iso 9 adum5200 t o p view (not to scale) 07540-006 nc = no connect figure 6. adum5200 pin configurati on table 21. adum5200 pin function descriptions pin no. mnemonic description 1 v dd1 primary supply voltage , 3.0 v to 5.5 v. 2, 8 gnd 1 ground 1. gr ound reference for the isolator primary side. pin 2 and pin 8 are internally connected to each other, and it is recommended that both pins be connected to a common ground. 3 v ia logic input a. 4 v ib logic input b. 5 rc in regulation control input. this p in must be connected to the rc out pin of a master iso power device or tied low. note that t his pin must not be tied high if rc sel is low; this combination causes excessive voltage on the secondary side, damaging the adum5200 and possibly the devices that it powers. 6 rc sel control input. determines self - regulation mode (rc sel high) or slave mode (rc sel low) , allowing external regulation. this pin is weakly pulled to the high state. in noisy environments, tie t his pin either high or low. 7, 12 nc no internal connection. 9, 15 gnd iso ground reference for isolator side 2. pin 9 and pin 15 are internally connected to each other, and it is recommended that both pins be connected to a common ground. 10 v e2 data en able input. when this pin is high or no t connect ed , the secondary outputs are active; when this pin is low, the outputs are in a high - z state. 11 v sel output voltage selection. when v sel = v iso , the v iso setpoint is 5.0 v. when v sel = gnd iso , the v iso set point is 3.3 v. in slave regulation mode, this pin has no function. 13 v ob logic output b. 14 v oa logic output a. 16 v iso secondary supply voltage. output for secondary side isolated data channels and external loads.
data sheet adum5200/adum5201/adum5202 rev. b | page 13 of 28 v dd1 1 gnd 1 2 v ia 3 v ob 4 v iso 16 gnd iso 15 v oa 14 v ib 13 rc in 5 nc = no connect nc 12 rc se l 6 v se l 1 1 v e1 7 v e2 10 gnd 1 8 gnd iso 9 adum5201 t op view (not to scale) 07540-007 figure 7. adum5201 pin configuration table 22. adum5201 pin function descriptions pin no. mnemonic description 1 v dd1 primary supply volta ge , 3.0 v to 5.5 v. 2, 8 gnd 1 ground 1. ground reference for isolator primary side. pin 2 and pin 8 are internally connected to each other, and it is recommended that both pins be connected to a common ground. 3 v ia logic input a. 4 v ob logic output b. 5 rc in regulation control input. this pin must be connected to the rc out pin of a master iso power device or tied low. note that t his pin must not be tied high if rc sel is low; this combination causes excessive voltage on the secondary side, damaging the adum5201 and possibly the devices that it powers. 6 rc sel control input. determines self - regulation mode (rc sel high) or slave mode (rc sel low) , allowing external regulation. this pin is weakly pulled to the high state. in noisy environments, tie this pin either high or low. 7 v e1 data enable input. when this pin is high or no t connect ed , the primary output i s active; when this pin is low, the output i s in a high - z state. 9, 15 gnd iso ground reference for is olator side 2. pin 9 and pin 15 are internally connected to each other, and it is recommended that both pins be connected to a common ground. 10 v e2 data enable input. when this pin is high or no t connect ed , the secondary output i s active; when this pin i s low, the output i s in a high - z state. 11 v sel output voltage selection. when v sel = v iso , the v iso setpoint is 5.0 v. when v sel = gnd iso , the v iso setpoint is 3.3 v. in slave regulation mode, this pin has no function. 12 nc no internal connection. 13 v ib logic input b. 14 v oa logic output a. 16 v iso secondary supply voltage. output for secondary side isolated data channels and external loads.
adum5200/adum5201/adum5202 data sheet rev. b | page 14 of 28 v dd1 1 gnd 1 2 v oa 3 v ob 4 v iso 16 gnd iso 15 v ia 14 v ib 13 rc in 5 nc 12 rc sel 6 v sel 11 v e1 7 nc 10 gnd 1 8 gnd iso 9 adum5202 top view (not to scale) 07540-008 nc = no connect figure 8. adum5202 pin config uration table 23. adum5202 pin function descriptions pin no. mnemonic description 1 v dd1 primary supply voltage , 3.0 v to 5.5 v. 2, 8 gnd 1 ground 1. ground reference for the isolato r primary side . pin 2 and pin 8 are internally connected to each other, and it is recommended that both pins be connected to a common ground. 3 v oa logic output a. 4 v ob logic output b. 5 rc in regulation control input. this pin must be connected to the rc out pin of a master iso power device or tied low. note that t his pin must not be tied high if rc sel is low; this combination causes excessive voltage on the secondary side, damaging the adum5202 and possibl y the devices that it powers. 6 rc sel control input. determines self - regulation mode (rc sel high) or slave mode (rc sel low) , allowing external regulation. this pin is weakly pulled to the high state. in noisy environments, tie this pin either high or low. 7 v e1 data enable input. when this pin is high or no t connect ed , the primary output i s active; when this pin is low, the output i s in a high - z state. 9, 15 gnd iso ground reference for isolator side 2. pin 9 and pin 15 are internally connected to each ot her, and it is recommended that both pins be connected to a common ground. 10, 12 nc no internal connection. 11 v sel output voltage selection. when v sel = v iso , the v iso setpoint is 5.0 v. when v sel = gnd iso , the v iso setpoint is 3.3 v. in slave regulat ion mode, this pin has no function. 13 v ib logic input b. 14 v ia logic input a. 16 v iso secondary supply voltage. output for secondary side isolated data channels and external loads. truth table table 24. power section truth t able (positive logic) 1 rc sel input rc in input v sel input v dd1 input (v) 2 v iso (v) operation h x h 5 .0 5 .0 self regulation mode, normal operation . h x l 5 .0 3.3 self regulation mode, normal operation . h x l 3.3 3.3 self regulation mode, normal operat ion . h x h 3.3 5 .0 this supply configuration is not recommended due to extremely poor efficiency . l h x x x part runs at max imum open - loop voltage ; therefore, damage can occur . l l x x 0 power supply is disabled . l rc out(ext) x x x slave mode, rc out(e xt) supplied by a master iso power device . 1 h refers to a high logic, l refers to a low logic, and x is dont care or unknown. 2 v dd1 must be common between all iso power devices being regulated by a master iso power part.
data sheet adum5200/adum5201/adum5202 rev. b | page 15 of 28 typical performance characteristics 0 5 10 15 20 25 30 35 40 0 0.02 0.04 0.06 0.08 0.10 0.12 07540-022 output current (a) efficienc y (power in/power out) (%) 3.3v input/3.3v output 5v input/3.3v output 5v input/5v output figure 9. typical power supply efficiency in all supported power configuration s 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.02 0.04 0.06 0.08 0.10 0.12 i iso (a) power dissi pa tion (w) v dd1 = 5 v , v iso = 5v v dd1 = 5 v , v iso = 3.3v v dd1 = 3.3 v , v iso = 3.3v 07540-023 figure 10 . typical total power dissipation vs. isolated output supply current in all supported power configuration s 0 0.02 0.04 0.06 0.08 0.10 0.12 0 0.05 0.10 0.15 0.20 0.25 0.35 0.30 input current (a) output current (a) 07540-024 3.3v input/3.3v output 5v input/3.3v output 5v input/5v output figure 11 . typical isolated output supply current vs. input current in all supported power configuration s 07540-011 0 0.5 1.0 1.5 2.0 3.0 2.5 3.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd1 (v) i dd1 (a) and power (w) power dissipation i dd figure 12 . typical sh ort - circuit input current and power vs. v dd1 supply voltage 07540-012 (100s/div) output voltage (500mv/div) dynamic load 10% load 90% load figure 13 . typical v iso transient load response, 5 v output, 10% to 90% load step 07540-013 (100s/div) output voltage (500mv/div) dynamic load 10% load 90% load figure 14 . typical v iso transient load response, 3 v o utput, 10% to 90% load step
adum5200/adum5201/adum5202 data sheet rev. b | page 16 of 28 07540-014 time (s) 0 0.5 1.0 25 20 15 10 5 0 ?5 1.5 2.0 2.5 3.0 3.5 4.0 5v output ripple (mv) bw = 20mhz figure 15 . typical output voltage ripple at 90% load , v iso = 5 v 07540-015 time (s) 0 0.5 1.0 16 14 12 10 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 3.3v output ripple (mv) bw = 20mhz figure 16 . typical output voltage ripple at 90% load , v iso = 3.3 v 07540-027 time (ms) v iso (v) 7 6 5 4 3 2 1 0 ?1 0 1 2 3 90% load 10% load figure 17 . typical output voltage start-u p transient at 10% and 90% load , v iso = 5 v 07540-028 time (ms) v iso (v) 5 4 3 2 1 0 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 90% load 10% load figure 18 . typical output voltage start-u p transient at 10% and 90% load , v iso = 3.3 v 0 4 8 12 16 20 0 5 10 15 d at a r a te (mbps) supply current (ma) 20 25 07540-025 5v input/5v output 3.3v input/3.3v output 5v input/3.3v output figure 19 . typical i ch n supply current per forward data channel (15 pf output load) 0 4 8 12 16 20 0 5 10 15 data rate (mbps) supply current (ma) 20 25 5v input/5v output 3.3v input/3.3v output 5v input/3.3v output 07540-026 figure 20 . typical i ch n supply current per reverse data channel (15 pf output load)
data sheet adum5200/adum5201/adum5202 rev. b | page 17 of 28 0 1 2 3 4 5 0 5 1 0 data rate (mbps) current (ma) 1 5 2 0 2 5 3.3v 5v 07540-018 figure 21 . typical i iso (d) dynamic supply curren t per input 0 1.0 0.5 1.5 2.0 2.5 3.0 0 5 1 0 data rate (mbps) current (ma) 1 5 2 0 2 5 3.3v 5v 07540-019 figure 22 . typical i iso (d) dynamic supply current per output (15 pf output load)
adum5200/adum5201/adum5202 data sheet rev. b | page 18 of 28 terminology i dd1 (q) i dd1 (q) is the minimum operating current drawn at the v dd1 pin when there is no external load at v iso and the i/o pins are operating below 2 mbps, requiring no additional dynamic supply current. i dd1 (q) reflects the minimum current operating condition. i dd1 ( d) i dd1 ( d ) is the typical input supply current with all channels simultaneously driven at a maximum data rate of 25 mbps with full capacitive load representing the maximum dynamic load conditions. resistive loads on the outputs should be treated separately from the dynamic load. i dd1 ( max ) i dd1 (max) is the input current under full dynamic and v iso load conditions. i so (load) i so (load) is the current available to the load. t phl propagation delay t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagat ion delay t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. propagation delay skew , t psk t psk is the magnitude of the worst - case difference in t phl and/or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. channel -to - channel matching , t pskcd /t pskod channel - to - channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads. minimum pulse width the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. maximum data rate the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
data sheet adum5200/adum5201/adum5202 rev. b | page 19 of 28 applications information the dc-to-dc converter section of the adum5200/ adum5201 / adum5202 works on principles that are common to most switching power supplies. it has a secondary side controller architecture with isolated pulse-width modulation (pwm) feedback. v dd1 power is supplied to an oscillating circuit that switches current into a chip scale air core transformer. power transferred to the secondary side is rectified and regulated to either 3.3 v or 5 v. the secondary (v iso ) side controller regulates the output by creating a pwm control signal that is sent to the primary (v dd1 ) side by a dedicated i coupler data channel. the pwm modulates the oscillator circuit to control the power being sent to the secondary side. feedback allows for significantly higher power and efficiency. the adum5200 / adum5201/ adum5202 implements under- voltage lockout (uvlo) with hysteresis on the v dd1 power input. this feature ensures that the converter does not enter oscillation due to noisy input power or slow power-on ramp rates. the adum5200 / adum5201 / adum5202 can accept an external regulation control signal (rc in ) that can be connected to other iso power devices. this allows a single regulator to control multiple power modules without contention. when accepting control from a master power module, the v iso pins can be connected together, adding their power. because there is only one feedback control path, the supplies work together seamlessly. the adum5200/ adum5201/ adum5202 can only regulate themselves or accept regulation (as slave devices) from another device in this product line; they cannot provide a regulation signal to other devices. pcb layout the adum5200 / adum5201/ adum5202 digital isolators with 0.5 w iso power, integrated dc-to-dc converter require no external interface circuitry for the logic interfaces. power supply bypassing is required at the input and output supply pins (see figure 23). note that low esr bypass capacitors are required between pin 1 and pin 2 and between pin 15 and pin 16, as close to the chip pads as possible. the power supply section of the adum5200/ adum5201/ adum5202 uses a 180 mhz oscillator frequency to pass power efficiently through its chip scale transformers. in addition, the normal operation of the data section of the i coupler introduces switching transients on the power supply pins. bypass capacitors are required for several operating frequencies. noise suppression requires a low inductance, high frequency capacitor, whereas ripple suppression and proper regulation require a large value capacitor. these capacitors are most conveniently connected between pin 1 and pin 2 for v dd1 and between pin 15 and pin 16 for v iso . to suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. the recommended capacitor values are 0.1 f and 10 f for v dd1 . the smaller capacitor must have a low esr; for example, use of a ceramic capacitor is advised. note that the total lead length between the ends of the low esr capacitor and the input power supply pin must not exceed 2 mm. installing the bypass capacitor with traces more than 2 mm in length may result in data corruption. consider bypassing between pin 1 and pin 8 and between pin 9 and pin 16 unless both common ground pins are connected together close to the package. v dd1 bypass < 2mm gnd 1 v ia /v oa v ib /v ob v iso gnd iso v oa /v ia v ob /v ib nc v sel rc in rc sel v e1 /nc v e2 /nc gnd 1 gnd iso 07540-020 figure 23. recommended pcb layout in applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. furthermore, design the board layout such that any coupling that does occur affects all pins equally on a given component side. failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings for the device (specified in table 19), thereby leading to latch-up and/or permanent damage. the adum5200 / adum5201 / adum5202 is a power device that dissipates approximately 1 w of power when fully loaded and running at maximum speed. because it is not possible to apply a heat sink to an isolation device, the device primarily depends on heat dissipation into the pcb through the gnd pins. if the device is used at high ambient temperatures, provide a thermal path from the gnd pins to the pcb ground plane. the board layout in figure 23 shows enlarged pads for pin 2, pin 8, pin 9, and pin 15. multiple vias should be implemented from the pad to the ground plane to significantly reduce the temperature inside the chip. the dimensions of the expanded pads are at the discretion of the designer and depend on the available board space. start-up behavior the adum5200 / adum5201 / adum5202 do not contain a soft start circuit. take the start-up current and voltage behavior into account when designing with this device. when power is applied to v dd1 , the input switching circuit begins to operate and draw current when the uvlo minimum voltage is reached. the switching circuit drives the maximum available power to the output until it reaches the regulation voltage where pwm control begins. the amount of current and time this takes depends on the load and the v dd1 slew rate. with a fast v dd1 slew rate (200 s or less), the peak current draws up to 100 ma/v of v dd1 . the input voltage goes high faster than the output can turn on; therefore, the peak current is proportional to the maximum input voltage.
adum5200/adum5201/adum5202 data sheet rev. b | page 20 of 28 with a slow v dd1 slew rate (in the millisecond range), the input voltage is not changing quickly when v dd1 reaches the uvlo minimum voltage. the current surge is approximately 300 ma because v dd1 is nearly constant at the 2.7 v uvlo voltage. the behavior during startup is similar to when the device load is a short circuit; these values are consistent with the short-circuit current shown in figure 12. when starting the device for v iso = 5 v operation, do not limit the current available to the v dd1 power pin to less than 300 ma. the adum5200 / adum5201 / adum5202 devices may not be able to drive the output to the regulation point if a current-limiting device clamps the v dd1 voltage during startup. as a result, the adum5200 / adum5201 / adum5202 devices can draw large amounts of current at low voltage for extended periods of time. the output voltage of the adum5200 / adum5201 / adum5202 exhibits v iso overshoot during startup. if this could potentially damage components attached to v iso , then a voltage-limiting device, such as a zener diode, can be used to clamp the voltage. typical behavior is shown in figure 17 and figure 18. emi considerations the dc-to-dc converter section of the adum5200 / adum5201 / adum5202 devices must operate at 180 mhz to allow efficient power transfer through the small transformers. this creates high frequency currents that can propagate in circuit board ground and power planes, causing edge emissions and dipole radiation between the primary and secondary ground planes. grounded enclosures are recommended for applications that use these devices. if grounded enclosures are not possible, follow good rf design practices in the layout of the pcb. see the an-0971 application note for board layout recommendations. propagation delay parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. the propagation delay to a logic low output may differ from the propagation delay to a logic high. input ( v ix ) output (v ox ) t plh t phl 50% 50% 07540-118 figure 24. propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately timing of the input signal is preserved. channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single adum5200 / adum5201 / adum5202 component. propagation delay skew refers to the maximum amount the propagation delay differs between multiple adum5200 / adum5201 / adum5202 components operating under the same conditions. dc correctness and magnetic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. the decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions at the input for more than 1 s, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. if the decoder receives no internal pulses of more than about 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see table 24) by the watchdog timer circuit. the limitation on the magnetic field immunity of the adum5200 / adum5201 / adum5202 is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large to either falsely set or reset the decoder. the following analysis defines the conditions under which this may occur. the 3 v operating condition of the adum5200 / adum5201 / adum5202 is examined because it represents the most susceptible mode of operation. the pulses at the transformer output have an amplitude greater than 1.0 v. the decoder has a sensing threshold at about 0.5 v, thus establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ?d/dt )? r n 2 ; n = 1, 2, , n where: is the magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the n th turn in the receiving coil (cm). given the geometry of the receiving coil in the adum5200 / adum5201 / adum5202 and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 25. magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 07540-119 figure 25. maximum allowable external magnetic flux density
data sheet adum5200/adum5201/adum5202 rev. b | page 21 of 28 for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event occurs during a transmitted pulse (and is of the worst-case polarity), it reduces the received pulse from >1.0 v to 0.75 vstill well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances from the adum5200/ adum5201/ adum5202 transformers. figure 26 expresses these allowable current magnitudes as a function of frequency for selected distances. as shown, the adum5200 / adum5201/ adum5202 are extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. for the 1 mhz example noted, a 0.5 ka current placed 5 mm away from the adum5200 / adum5201 / adum5202 is required to affect the operation of the component. magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 07540-120 figure 26. maximum allowable current for various current-to- adum5200 / adum5201 / adum5202 spacings note that at combinations of strong magnetic field and high frequency, any loops formed by pcb traces can induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. exercise care in the layout of such traces to avoid this possibility. power consumption the v dd1 power supply input provides power to the i coupler data channels as well as to the power converter. for this reason, the quiescent currents drawn by the data converter and the primary and secondary input/output channels cannot be determined sepa- rately. all of these quiescent power demands have been combined into the i dd1 (q) current shown in figure 27. the total i dd1 supply current is the sum of the quiescent operating current, dynamic current i dd1 (d) demanded by the i/o channels, and any external i iso load. 07540-021 converter primary i dd1(q) i iso i dd1(d) i ddp(d) i iso(d) converter secondary primary data i/o 2-channel secondary data i/o 2-channel figure 27. power consumption within the adum5200 / adum5201 / adum5202 both dynamic input and output current is consumed only when operating at channel speeds higher than the rate of f r . because each channel has a dynamic current determined by its data rate, figure 19 shows the current for a channel in the forward direction, which means that the input is on the primary side of the part. figure 20 shows the current for a channel in the reverse direction, which means that the input is on the secondary side of the part. both figures assume a typical 15 pf load. the following relationship allows the total i dd1 current to be calculated: i dd1 = ( i iso v iso )/( e v dd1 ) + i chn ; n = 1 to 4 (1) where: i dd1 is the total supply input current. i chn is the current drawn by a single channel determined from figure 19 or figure 20, depending on channel direction. i iso is the current drawn by the secondary side external loads. e is the power supply efficiency at 100 ma load from figure 9 at the v iso and v dd1 condition of interest. calculate the maximum external load by subtracting the dynamic output load from the maximum allowable load. i iso (load) = i iso (max) ? i iso (d)n ; n = 1 to 4 (2) where: i iso (load) is the current available to supply an external secondary side load. i iso (max) is the maximum external secondary side load current available at v iso . i iso (d)n is the dynamic load current drawn from v iso by an input or output channel, as shown in figure 19 and figure 20. data is presented assuming a typical 15 pf load. the preceding analysis assumes a 15 pf capacitive load on each data output. if the capacitive load is larger than 15 pf, the addi- tional current must be included in the analysis of i dd1 and i iso (load) . to d e te r m i n e i dd1 in equation 1, additional primary side dynamic output current (i aod ) is added directly to i dd1 . additional secondary side dynamic output current (i aod ) is added to i iso on a per-channel basis. to d e te r m i n e i iso (load) in equation 2, additional secondary side output current (i aod ) is subtracted from i iso (max) on a per-channel basis.
adum5200/adum5201/adum5202 data sheet rev. b | page 22 of 28 for each output channel with c l greater than 15 pf, the additional capacitive supply current is given by i aod = 0.5 10 ?3 (( c l ? 15) v iso ) (2 f ? f r ); f > 0.5 f r (3) where: c l is the output load capacitance (pf). v iso is the output supply voltage (v). f is the input logic signal frequency (mhz); it is half of the input data rate expressed in units of mbps. f r is the input channel refresh rate (mbps). current limit and thermal overload protection the adum5200 / adum5201/ adum5202 are protected against damage due to excessive power dissipation by thermal overload protection circuits. thermal overload protection limits the junction temperature to a maximum of 150c (typical). under extreme conditions (that is, high ambient temperature and power dissipation), when the junction temperature starts to rise above 150c, the pwm is turned off, reducing the output current to zero. when the junction temperature drops below 130c (typical), the pwm turns on again, restoring the output current to its nominal value. consider the case where a hard short from v iso to ground occurs. at first, the adum5200 / adum5201 / adum5202 reach their maximum current, which is proportional to the voltage applied at v dd1 . power dissipates on the primary side of the converter (see figure 12). if self-heating of the junction becomes great enough to cause its temperature to rise above 150c, thermal shutdown activates, turning off the pwm, and reducing the output current to zero. as the junction temperature cools and drops below 130c, the pwm turns on, and power dissipates again on the primary side of the converter, causing the junction temperature to rise to 150c again. this thermal oscillation between 130c and 150c causes the part to cycle on and off as long as the short remains at the output. thermal limit protections are intended to protect the device against accidental overload conditions. for reliable operation, externally limit device power dissipation to prevent junction temperatures from exceeding 130c. power considerations the adum5200 / adum5201 / adum5202 power input, data input channels on the primary side and data input channels on the secondary side are all protected from premature operation by uvlo circuitry. below the minimum operating voltage, the power converter holds its oscillator inactive and all input channel drivers and refresh circuits are idle. outputs remain in a high impedance state to prevent transmission of undefined states during power-up and power-down operations. during application of power to v dd1 , the primary side circuitry is held idle until the uvlo preset voltage is reached. at that time, the data channels initialize to their default low output state until they receive data pulses from the secondary side. when the primary side is above the uvlo threshold, the data input channels sample their inputs and begin sending encoded pulses to the inactive secondary output channels. the outputs on the primary side remain in their default low state because no data comes from the secondary side inputs until secondary power is established. the primary side oscillator also begins to operate, transferring power to the secondary power circuits. the secondary v iso voltage is below its uvlo limit at this point; the regulation control signal from the secondary is not being generated. the primary side power oscillator is allowed to free run in this circumstance, supplying the maximum amount of power to the secondary, until the secondary voltage rises to its regulation setpoint. this creates a large inrush current transient at v dd1 . when the regulation point is reached, the regulation control circuit produces the regulation control signal that modulates the oscillator on the primary side. the v dd1 current is reduced and is then proportional to the load current. the inrush current is less than the short-circuit current shown in figure 12. the duration of the inrush current depends on the v iso loading conditions and the current available at the v dd1 pin. as the secondary side converter begins to accept power from the primary, the v iso voltage starts to rise. when the secondary side uvlo is reached, the secondary side outputs are initialized to their default low state until data is received from the correspond- ing primary side input. it can take up to 1 s after the secondary side is initialized for the state of the output to correlate with the primary side input. secondary side inputs sample their state and transmit it to the primary side. outputs are valid about 1 s after the secondary side becomes active. because the rate of charge of the secondary side power supply is dependent on loading conditions and the input voltage level and the output voltage level selected, take care with the design to allow the converter sufficient time to stabilize before valid data is required. when power is removed from v dd1 , the primary side converter and coupler shut down when the uvlo level is reached. the secondary side stops receiving power and starts to discharge. the outputs on the secondary side hold the last state that they received from the primary side. either the uvlo level is reached and the outputs are placed in their high impedance state, or the outputs detect a lack of activity from the primary side inputs and the outputs are set to their default low value before the secondary power reaches uvlo.
data sheet adum5200/adum5201/adum5202 rev. b | page 23 of 28 thermal analysis the adum5200 / adum5201 / adum5202 consist of four internal die, attached to a split lead frame with two die attach paddles. for the purposes of thermal analysis, it is treated as a thermal unit with the highest ju nction temperature reflected in the ja value in table 14 . the value of ja is based on measurements taken with the part mounted on a jedec standard 4 - layer board with fine width traces and still air. under normal operating conditions, the adum5200 / adum5201 / adum5202 operate at full load across the full temperature range without derating the output current. how ever, following the recommendations in the pcb layout section decreases the thermal resistance to the pcb , allowing increased thermal margin at high ambient temperatures. increasing available power the adum5200 / adum5201 / adum5202 are designed with the capability of running in combination with other compatible iso power devices . the rc in and rc sel pins allow the adum5200 / adum5201 / adum5202 to receive a pwm signal from another device thro ugh the rc in pin and act as a slave to that control signal. the rc sel pin chooses whether the part acts as a stand - alone self - regulated device or a slave device. when the adum5200 / adum5201 / adum5202 act as a slave, their power is regulated by a pwm signal coming from a master device. this allows multiple iso power parts to be combined in parallel while sharing the loa d equally. when the adum5200 / adum5201 / adum5202 are configured as standalone unit s, they generate their own pwm feedback signal to regulate them sel ves . the adum5000 can act as a master or a slave device, the adum5401 , adum54 02, adum5403 , and adum5404 can only be master/standalone, and the adum520x can only be a slave/standalone devi ce. this means that the adum5000 , adum520x , and adum5401 to adum5 404 can only be used in certain master/slave combinations as listed in table 25. table 25 . allowed combinations of iso power parts master slave adum5000 adum520x adum5401 to adum5404 adum5000 yes yes no adum520x no no no adum5401 to adum5404 yes yes no the allowed combinations of master and slave configured par ts listed in table 25 is sufficient to make any combination of power and channel count. table 26 illustrates how iso power devices can provide many combinations of data channel count and mu ltiples of the single unit power. table 26 . configurations for power and data channels power units number of data channels 0 channels 2 channels 4 channels 6 channels 1 - unit power adum5000 master adum520x master adum5401 to adum5404 master adum540 1 to adum5404 master adum121x 2 - unit power adum5000 master ad um5000 master adum5401 to adum5404 master adum5401 to adum5404 master adum5000 slave adum520x slave adum520x slave adum520x slave 3 - unit power adum5000 master adum5000 master adum5401 to adum5404 master adum5401 to adum5404 master adum5000 slave adum5000 s lave adum5000 slave adum520x slave adum5000 slave adum520x slave adum5000 slave adum5000 slave
adum5200/adum5201/adum5202 data sheet rev. b | page 24 of 28 insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. in addition to the testing performed by the regulatory agencies, analog devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the adum5200 / adum5201 / adum5202 . analog devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. acceleration factors for several operating conditions are determined. these factors allow calculation of the time to failure at the actual working voltage. the values shown in table 20 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum csa/vde approved working voltages. in many cases, the approved working voltage is higher than a 50-year service life voltage. operation at these high working voltages can lead to shortened insulation life in some cases. the insulation lifetime of the adum5200 / adum5201 / adum5202 depends on the voltage waveform type imposed across the isolation barrier. the i coupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 28, figure 29, and figure 30 illustrate these different isolation voltage waveforms. bipolar ac voltage is the most stringent environment. the goal of a 50-year operating lifetime under the ac bipolar condition determines the maximum working voltage recommended by analog devices. in the case of unipolar ac or dc voltage, the stress on the insula- tion is significantly lower. this allows operation at higher working voltages while still achieving a 50-year service life. the working voltages listed in table 20 can be applied while maintaining the 50-year minimum lifetime, provided the voltage conforms to either the unipolar ac or dc voltage cases. any cross-insulation voltage waveform that does not conform to figure 29 or figure 30 should be treated as a bipolar ac waveform and its peak voltage limited to the 50-year lifetime voltage value listed in table 20. the voltage presented in figure 29 is shown as sinusoidal for illustration purposes only. it is meant to represent any voltage waveform varying between 0 v and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0 v. 0v rated peak voltage 07540-121 figure 28. bipolar ac waveform 0v rated peak voltage 07540-122 figure 29. unipolar ac waveform 0v rated peak voltage 07540-123 figure 30. dc waveform
data sheet adum5200/adum5201/adum5202 rev. b | page 25 of 28 outline dimensions controlling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded-off millimeter equiv alents for reference onl y and are not appropria te for use in design. compliant t o jedec st andards ms-013-aa 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.01 18) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.02 01) 0.31 (0.0122) sea ting plane 8 0 1 6 9 8 1 1.27 (0.0500) bsc 03-27-2007-b figure 31 . 16 - lead standard small outline packa ge [soic_w] wide body (rw - 16) dimensions shown in millimeters and (inches) ordering guide model 1 , 2 number of inputs, v dd1 side number of inputs, v dd2 side maximum data rate (mbps) maximum propagation delay, 5 v (ns) maximum pulse width distortion ( ns) temperature range package description package option adum5200arwz 2 0 1 100 40 ?40c to +105c 16- lead soic_w rw -16 adum5200crwz 2 0 25 70 3 ?40c to +105c 16- lead soic_w rw -16 adum5201arwz 1 1 1 100 40 ?40c to +105c 16- lead soic_w rw -16 adum5201crwz 1 1 25 70 3 ?40c to +105c 16- lead soic_w rw -16 adum5202arwz 0 2 1 100 40 ?4 0c to +105c 16- lead soic_w rw -16 ADUM5202CRWZ 0 2 25 70 3 ?40c to +105c 16- lead soic_w rw -16 1 z = rohs compliant part. 2 tape and reel are available. the additional - rl suffix designates a 13 - inch (1,000 units) tape and re el option.
adum5200/adum5201/adum5202 data sheet rev. b | page 26 of 28 notes
data sheet adum5200/adum5201/adum5202 rev. b | page 27 of 28 notes
adum5200/adum5201/adum5202 data sheet rev. b | page 28 of 28 notes ? 2009 - 2012 analog devices, inc. all rights reserved. trademarks and registered tr ademarks are the property of their respective owners. d07540 - 0- 5/12(b)

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